diff --git a/arch/arm/dts/socfpga_arria10-handoff.dtsi b/arch/arm/dts/socfpga_arria10-handoff.dtsi
index c083716..a3afb4d 100644
--- a/arch/arm/dts/socfpga_arria10-handoff.dtsi
+++ b/arch/arm/dts/socfpga_arria10-handoff.dtsi
@@ -4,14 +4,14 @@
 	clocks {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 
 		altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 			clock-frequency = <EOSC1_CLK_HZ>;
 			clock-output-names = "altera_arria10_hps_eosc1-clk";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
@@ -19,7 +19,7 @@
 			#clock-cells = <0>;
 			clock-frequency = <CB_INTOSC_LS_CLK_HZ>;
 			clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		/* Clock source: altera_arria10_hps_f2h_free */
@@ -28,7 +28,7 @@
 			#clock-cells = <0>;
 			clock-frequency = <F2H_FREE_CLK_HZ>;
 			clock-output-names = "altera_arria10_hps_f2h_free-clk";
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 	};
 
@@ -36,7 +36,7 @@
 		compatible = "altr,socfpga-a10-clk-init";
 		reg = <0xffd04000 0x00000200>;
 		reg-names = "soc_clock_manager_OCP_SLV";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 
 		mainpll {
 			vco0-psrc = <MAINPLLGRP_VCO0_PSRC>;
@@ -63,7 +63,7 @@
 			nocdiv-csatclk = <MAINPLLGRP_NOCDIV_CSATCLK>;
 			nocdiv-cstraceclk = <MAINPLLGRP_NOCDIV_CSTRACECLK>;
 			nocdiv-cspdbgclk = <MAINPLLGRP_NOCDIV_CSPDBGCLK>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		perpll {
@@ -88,13 +88,13 @@
 			emacctl-emac1sel = <PERPLLGRP_EMACCTL_EMAC1SEL>;
 			emacctl-emac2sel = <PERPLLGRP_EMACCTL_EMAC2SEL>;
 			gpiodiv-gpiodbclk = <PERPLLGRP_GPIODIV_GPIODBCLK>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		alteragrp {
 			nocclk = <ALTERAGRP_NOCCLK>;
 			mpuclk = <ALTERAGRP_MPUCLK>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 	};
 
@@ -104,7 +104,7 @@
 		compatible = "pinctrl-single";
 		reg = <0xffd07000 0x00000800>;
 		reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 
 		shared {
 			reg = <0xffd07000 0x00000200>;
@@ -159,7 +159,7 @@
 				<0x000000b4 PINMUX_SHARED_IO_Q4_10_SEL>,
 				<0x000000b8 PINMUX_SHARED_IO_Q4_11_SEL>,
 				<0x000000bc PINMUX_SHARED_IO_Q4_12_SEL>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		dedicated {
@@ -181,7 +181,7 @@
 				<0x00000038 PINMUX_DEDICATED_IO_15_SEL>,
 				<0x0000003c PINMUX_DEDICATED_IO_16_SEL>,
 				<0x00000040 PINMUX_DEDICATED_IO_17_SEL>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		dedicated_cfg {
@@ -207,7 +207,7 @@
 				<0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>,
 				<0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>,
 				<0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 
 		fpga {
@@ -232,7 +232,7 @@
 				<0x00000038 PINMUX_SPIS1_USEFPGA_SEL>,
 				<0x0000003c PINMUX_UART0_USEFPGA_SEL>,
 				<0x00000040 PINMUX_UART1_USEFPGA_SEL>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 	};
 
@@ -240,7 +240,7 @@
 		compatible = "altr,socfpga-a10-noc";
 		reg = <0xffd10000 0x00008000>;
 		reg-names = "mpu_m0";
-		u-boot,dm-pre-reloc;
+		bootph-all;
 
 		firewall {
 			mpu0 = <0x00000000 0x0000ffff>;
@@ -248,43 +248,43 @@
 			fpga2sdram0-0 = <0x00000000 0x0000ffff>;
 			fpga2sdram1-0 = <0x00000000 0x0000ffff>;
 			fpga2sdram2-0 = <0x00000000 0x0000ffff>;
-			u-boot,dm-pre-reloc;
+			bootph-all;
 		};
 	};
 
 	hps_fpgabridge0: fpgabridge@0 {
 		compatible = "altr,socfpga-hps2fpga-bridge";
 		init-val = <H2F_AXI_MASTER>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 
 	hps_fpgabridge1: fpgabridge@1 {
 		compatible = "altr,socfpga-lwhps2fpga-bridge";
 		init-val = <LWH2F_AXI_MASTER>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 
 	hps_fpgabridge2: fpgabridge@2 {
 		compatible = "altr,socfpga-fpga2hps-bridge";
 		init-val = <F2H_AXI_SLAVE>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 
 	hps_fpgabridge3: fpgabridge@3 {
 		compatible = "altr,socfpga-fpga2sdram0-bridge";
 		init-val = <F2SDRAM0_AXI_SLAVE>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 
 	hps_fpgabridge4: fpgabridge@4 {
 		compatible = "altr,socfpga-fpga2sdram1-bridge";
 		init-val = <F2SDRAM1_AXI_SLAVE>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 
 	hps_fpgabridge5: fpgabridge@5 {
 		compatible = "altr,socfpga-fpga2sdram2-bridge";
 		init-val = <F2SDRAM2_AXI_SLAVE>;
-		u-boot,dm-pre-reloc;
+		bootph-all;
 	};
 };